The present invention relates to clock distribution circuitry, and more particularly, to low power clock distribution circuitry.
In integrated circuit designs, a clock distribution network (also referred to as a “clock tree”) consumes a considerable percentage of the total active power of the integrated circuit. Therefore, in the related art, a power savings technique referred to as “clock-gating” is widely applied to moderate overall power consumption within the integrated circuit.
The clock-gating technique reduces the power consumption of the clock distribution tree by disabling or “gating off” the clocks fed to some circuit units of the integrated circuit while those circuit units are not in use.
A problem with clock gating is that it requires additional logic (e.g., clock gating logic) and a control unit to manage the clock gating control signals. In order to have a net power savings, the clock gating logic must consume less power than is saved by gating the clocks off.
Unfortunately, the related art clock gating techniques do not provide significant power reduction when the integrated circuit is in full operation. That is, the power savings of the integrated circuit is not obvious or is limited when intensive processing is occurring and/or all circuit units of the integrated circuit are in use. Accordingly, a need exists for improving the power consumption of clock trees.